C, Spi, Verilog, I2c, Python, C++, Uart, Perl, Real Number Modeling, LNA, Analog IC design, LVS, Bias bandgap, VHDL, Cadence IC design tools, Filters, LDO, Layout experience using Cadence flow, VerilogAMS, Charge pump, Opamp, systemverilog, MIPI, DRC, VerilogA

Matlab, Worst case identification, Monte Carlo analysis, Block level topology selection, AMs, Analog Circuit Design, Spectre, Cadence tool set, Top level simulation, Simplis, IC system partitioning and architectural tradeoff analysis, Hand analysis and IC transistor level implementation, Post layout parasitic extraction, Schematic generation and simulation on modern CAD tools

references, analog mixed-signal IC design, ADCs, Cadence, mixed-signal design, PGAs, Spectre, DACs, Calibre, interfacing with microcontrollers, low-noise amplifiers, virtuoso, on-chip power blocks

Cadence Virtuoso, High-Speed ADC Design, EDA Tools, Post-silicon validation, Analog IC Design, Mixed-Signal IC Design

Pvs, Analog layout design, die-to-bump connectivity, package substrate interactions, PEX, R3D, analog layout matching techniques, EM, Ir, IC Layout design, LVS, CAD Tools, Floor Planning, Calibre, Xl, Esd, DRC, PowerFET, virtuoso, Packaging

Analog Circuit Design, Feedback Stability Fundamentals, Analog Layout, Power IC Fundamentals, MOSFET Physics, Debugging Problem Solving, Simulation Verification