boundary scan , static timing analysis, Vcs, Perl, Python, Tcl, Scan Insertion, sdf debugging, Jtag protocols, memory BIST, TetraMax, Verilog design, p1500, p1687, Tessent, ATPG, Gate level simulation, EDA Tools, Timing Closure, BIST architectures, timing based simulations, TestMax

System Verilog, Vcs, Logic Equivalency checking, Gate level simulation debugging, ATE patterns, Post-silicon validation, JTAG protocols, ATPG, Scan and BIST architectures

bist , boundary scan , DFT features, Scan Insertion, ATPG methodologies, advanced DFT techniques