System Verilog, Building test benches from scratch, ASIC verification using UVM, Gate Level Simulations

System Verilog, Gate Level Simulations, Building test benches from scratch, ASIC verification using UVM

Tcp, Pcie, Ethernet, System Verilog, Forwarding logic Parsers P4, RDMA, Palladium, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification, Building test benches

Tcp, System Verilog, Ethernet, Pcie, formal verification, Forwarding logic Parsers P4, Verifying sophisticated blocks clusters and top level for ASIC, Building test benches from scratch, RDMA, Zebu, System Verilog constraints structures and classes, HAPS, ASIC verification using UVM, Palladium, Veloce