Shell, Perl, Python, Tcl, power analysis, RTL simulation, Design Verification, clock gating, Uvm, GLS, activity analysis, Simulation emulation, power-aware verification, vector development, power states, Retention

Perl, Python, Tcl, FineSim, Matlab Simulink, Cadence Xcelium, CustomSim, mixed-signal verification, Uvm, systemverilog, Spectre, Synopsys VCS, AMS Designer, Cadence Virtuoso, Verilog-A

Java, Cassandra, Spring Boot, Kafka, J2EE, Spring Cloud, Google Cloud, Spring, Microservices, Jms, Docker, MySQL, Openshift, MongoDB, Oracle, Azure, Kubernetes, AWS, CI/CD

Unix, Lsf, Constraints, Jenkins, Git, Shell, Linux, Verilog, Gitlab, Python, Tcl, Synthesis, cdc, Simulation, RTL, make, systemverilog, RDC, UGE, LINT, CI/CD, Low Power, Slurm

Perl, Python, Tcl, primetime, RTL-to-GDS recipes, Physical Design, Fusion Compiler, Synopsys Fusion Design Platform, IC Compiler II, AI ML optimization tools, Synopsys DSO.ai

static timing analysis, Perl, shell scripting, Python, Tcl, LINT, Synthesis, cdc, SoC integration, UPF-based methodologies, ASIC SOC design, systemverilog, Dft, RTL Verilog, Bluetooth SoCs, low-power design

Static Timing Analysis (STA), PERL, Python, Tcl, Synthesis, Cadence

C, C++, Dac, Scripting, Python, LabVIEW, ADC, mixed-signal ICs, sensing solutions, lab instrumentation, AFE data-acquisition, analog signal-chains, embedded MCU, RISC-V, Pcb Design, reference designs, PGAs, evaluation boards, sensor excitation, low-noise amps, precision power supplies, ARM subsystems