Fcoe, spyglass, Verilog RTL coding, Synopsys Design Compiler, ASIC debugging, Multi-domain clock synchronization, High performance memory subsystems, High-speed serial interfaces, LEC, Networking protocols Ethernet, Verplex

Digital RTL Design, VHDL, Timing Analysis, Low-Power Design Techniques, Logic Synthesis, systemverilog

C, Vcs, Perl, Verilog, Scripting, C++, spyglass, cdc, Hardware Emulation Platforms, systemverilog, Rtl Design, EVE, Veloce, formal verification, LINT, Makefiles, Flow automation, Gate-level understanding, System Validation, SW HW bring-up, Synthesis, Implementation specification, System debug, Timing Analysis

Perl, Verilog, Python, Prototyping, Gdb, ASIC design flow, Rtl Design, Eco, Lab debug, Dft, VCS or equivalent simulation tools, Logic Synthesis, Bring-up, Debug tools like Debussy, Floor-planning, Verification, Timing Analysis

Networking Protocols, Ethernet, Fcoe, multi-domain clock synchronization, spyglass, high-speed serial interfaces, high performance memory subsystems, Verplex LEC, ASIC debugging, ASIC Design, Synopsys Design Compiler, Verilog RTL coding

Shell scripting, Static Timing Analysis, Tcl, Verilog, System Verilog, Ethernet, Python, Pcie, Perl, Git, Dft, Synthesis, AXI-based interconnects, LINT, cdc, Sta, CXL, RDC

Synthesis, ASIC Design, Rtl Design