Shell scripting, DFT verification, Memory BIST, Synopsys Tetramax DFTMAX, VCS simulation tool, IEEE1500, Mentor TestKompress, JTAG 1149.x, Verilog RTL design, Scan

Static Timing Analysis, MBIST insertion and simulation, DFT simulation with and without SDF, Characterization DC Characteristics, Formal verification tools, RTL based and netlist-based insertion flows, Boundary Scan inserting tap controller and P1500

Static timing analysis, Perl, Python, Tcl, ASIC DFX, DFx methodologies, Design Compiler, Fusion Compiler, BSCAN, MBIST, DFX Design Architect, SSN, Timing Closure, spyglass, Tessent, ATPG, EDT, Scan, ICl Extraction, TestKompress, IJTAG

Static timing analysis, Perl, Python, Tcl, ASIC DFX, DFx methodologies, Design Compiler, BSCAN, MBIST, DFX Design Architect, SSN, Timing Closure, Synthesis, spyglass, DFT implementation, Tessent, ATPG, Scan, TestKompress, IJTAG

Perl, Shell scripting, DFT verification, Synopsys Tetramax DFTMAX, VCS simulation tool, IEEE1500, Scan memory BIST, Verilog RTL design, JTAG 1149.x, Design for Test methodologies, Mentor testkompress