Dft, top-level timing closure flow, ATPG, Innovus hierarchical partition tools

Jira, Test Methodologies, Ethernet, Pcie, SFDC, Synthesis, jitter, Noise, UCIe, Tx and Rx Equalizers, board design, Verilog RTL design, Sta, ADC, gate level verification, Phase Locked Loops, DFT flows, AI-powered tools, case management systems

HDL - Verilog, Logic Design, Tcl, shell scripting, System Verilog, Perl, Synthesis, EDA Tools, Genus Synthesis Solution, low power design, Cadence Tools, Physical Design, formal verification, Timing Closure