Python, System Verilog, Perl, Uvm, formal verification, verification methodologies, constraint random verification, Profiling Tools, verification flows, coverage metrics

Tcl, Python, Perl, systemverilog, Functional coverage, Verification closure, Assertions, Uvm, Gate-level simulations, Siemens Questa/QuestaSim, Synopsys VCS, DMA engines, Protocol compliance, Performance verification techniques, Timing Analysis, Cadence Xcelium

rtl verification , Pcie, Nvme, systemverilog, Uvm, Axi, AHB, Asic verification

Shell scripting, Python, Vcs, Perl, systemverilog, Uvm, NC

AWS, Python, systemverilog, JasperGold, ISO 26262, VC Formal, Cloud formal execution, Rtl Design, SVA, Smart Proof, scripting for data integration, OneSpin, QuietTraceTM, VisualizeTM, Verification, safety security standards, PSL assertions, AI ML in EDA tools

C, Verilog, System Verilog, Debugging, Uart, Bash, Spi, Test Plan Creation, DDR, Pcie, Perl, I2c, Python, Tcl, Palladium emulation, DFX Verification, Uvm, FPGA prototyping, RTL simulations, Test-bench development, i2s, Gate-Level Simulations, Axi, APB, AHB

Tcl, Python, Perl, SVA, Uvm, Functional Coverage, ASIC SoC Subsystem IP verification, systemverilog