Logic Design, Physical design architecture, P R Timing and Physical verification tools, floorplanning, Physical implementation flows, Physical design flows

Electromigration (EM, Tcl, Python, Perl, Automation Frameworks, Timing Closure, Fusion Compiler, Synopsys DSO.ai, Sub-3nm device physics, primetime, Dynamic IR drop, Crosstalk challenges, Flows-as-Code, Physical Design and Methodology, Standard Cell SRAM library architectures, Tape-out experience with TSMC N3, CPU micro-architecture, Cerebrus, IC Compiler II, Synopsys Fusion Design Platform