Dft, scan-stitching, post silicon engineering, post-silicon bring up, Tessent ATPG, ATPG, VTPx, DVT environment

boundary scan , Jtag, MBIST, IEEE 1687, Testability Analysis, Scan Insertion, silicon debug, ATPG, LBIST, iJTAG, Compression

boundary scan , logic bist , DFT techniques, Memory BIST, Scan Insertion, Test Modes implementation and verification, IDDQ, Pin-muxing, Bridging fault generation, simulations at gate level, on-chip compression, high test coverage, SDD, At-speed Path delay, timing SDF, At-speed Scan Test-clocking, Scan On-Chip Compression, Test vector Stuck-at, Analog Testing

Perl, Tcl Scripting, Timing Formal verification, PD flow knowledge, ATPG Pattern generation, SCAN DRC Coverage debug, Dft, JTAG P1500 protocols, Gate level simulations, Zero delay Timing Delay simulations