Static Timing Analysis, MBIST insertion and simulation, DFT simulation with and without SDF, Characterization DC Characteristics, Formal verification tools, RTL based and netlist-based insertion flows, Boundary Scan inserting tap controller and P1500

Static timing analysis, Perl, Python, Tcl, ASIC DFX, DFx methodologies, Design Compiler, Fusion Compiler, BSCAN, MBIST, DFX Design Architect, SSN, Timing Closure, spyglass, Tessent, ATPG, EDT, Scan, ICl Extraction, TestKompress, IJTAG

Static timing analysis, Perl, Python, Tcl, ASIC DFX, DFx methodologies, Design Compiler, BSCAN, MBIST, DFX Design Architect, SSN, Timing Closure, Synthesis, spyglass, DFT implementation, Tessent, ATPG, Scan, TestKompress, IJTAG

Static timing analysis, MBIST, Synthesis, SSN, Timing Closure, BSCAN, Fusion Compiler, DFX Design Architect, ICl Extraction, ATPG, DFx methodologies, ASIC DFX, Scan, IJTAG, EDT, TestKompress