C, Python, Perl, MATLAB, Parasitic Extraction, High-speed SerDes circuits, systemverilog, Mixed-signal verification, Verilog-A, Cadence Virtuoso, RF ADE, Spectre

conformal lec , Unix, Clp, Linux, Tcl, Python, Perl, Cadence Genus, UPF, LEC, IEEE 1801, CPF-based power intent, low-power verification flows, ASIC synthesis

Perl, Tcl Scripting, Python, System Verilog, Synopsys Mentor VIPs, PCIe Gen3, random constraint-based testing, verification methodologies, performance power optimization, SMMU, CXL 1.1, Coresight architecture, assertion-based verification, Uvm, UPF, CHI protocols, Axi, formal verification, power-aware verification, coverage-driven testing, SVA

Tableau, Tcl, Powerbi, Ms Excel, Python, PERL, Ccsp, Sta, AOCV, EDA development, Layout Design, FinFET technologies, Standard Cell Circuit Design, RTL2GDS flow, NLDM, Circuit and MC simulations, LVF, characterization, PNR, Layout Dependent Effects, Skill, CCSN