Clp, automation, Scripting, prelayout STA, postlayout STA, LINT, low power aspects, Synthesis, cdc, SDC generation, demotion, SDC development, LEC, RTL Netlist based static checks, Dft, Timing Constraints, Timing Closure, Verification, promotion, equivalence checking

power optimization , Routing, Automation, Sta, Digital Synthesis, AOCV, RTL-to-GDS Flow, Signoff, Clock-Tree Analysis, EM, Physical Verification, Ir, floorplanning, CTS, Timing Constraints, Timing ECO Techniques, Clock Balancing, Placement, SOCV, Clock Latency, Timing Closure, Extraction

Tcl, Python, Perl, timing ECO generation, Timing Constraints, timing constraint validation, AOCV, timing convergence, UPF basics, cross-talk, STA fundamentals, noise process variation, UPF based static low power check, ASIC Back End flows, power optimization techniques, Signal Integrity, physical and UPF aware synthesis, POCV, power analysis