Dft, scan-stitching, post silicon engineering, post-silicon bring up, Tessent ATPG, ATPG, VTPx, DVT environment

memory test , Scripting Languages, Digital Logic Design, Hdl, Jtag, Static Timing Analysis, IEEE1500, BIST Architecture, Compression Techniques, IEEE1149.1, Eco, ASIC, Logic Design Flow, Scan ATPG, Gates Verification, Simulation