C, C++, Makefile, Windows, Shell, Linux, Verilog, System Verilog, Python, IP level ASIC verification, SystemVerilog language, acceleration HLS tools process, UVM testbenches, automating workflows in a distributed compute environment, UVM concepts, simulation profile efficiency improvement, debugging firmware and RTL code using simulation tools, UVM based verification frameworks, testbenches processes and flows

System Verilog, Verilog, Jasper, Synopsys VCS, Synopsys VC-Formal Magellan, Uvm, Cadence IES, Simulation Tools, Cadence IEV, Formal property checking tools