Debugging, C, Shell, Tcl, Verilog, System Verilog, Python, Perl, directed and constrained random methodologies, UVM methodology, Metric Driven Verification, functional and code coverage, assertions, formal verification methodologies

C, Perl, Verilog, Python, Tcl, formal verification, VHDL, Uvm, systemverilog, constrained-random verification

software security , Test automation, Sdlc, Agile, Selenium, Bdd, Test Strategy, AWS, Python, Azure, Tdd, Cloud Technologies, Automation Frameworks, Test Architecture, CI/CD, Quality Management System, Quality engineering practices

Systemc, Test Planning, C, Shell, Tcl, Verilog, Python, systemverilog, NoC bus and interconnect verification, assertions, transaction-level modeling, UVM-based testbench development, constrained-random verification, formal verification, power-aware verification