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Job Description:

Position Overview

We are seeking an accomplished and technically strong Technical Staff Engineer - Verification to provide technical leadership for the verification of next-generation Ethernet Switch and PCIe Switch SoCs. This role is focused on complex, high-performance designs integrating Ethernet, PCIe, ARM/MIPS CPU subsystems, and AMBA-based interconnect fabrics (AXI/AHB/APB).

The ideal candidate will drive verification strategy and execution across IP, subsystem, and full-SoC levels using SystemVerilog UVM as the primary verification methodology. This role requires deep expertise in scalable verification architecture, coverage-driven methodologies, protocol compliance, and system-level debug.

As a senior technical leader, the candidate will influence verification methodologies, mentor engineers across teams, collaborate with architecture and design leadership, and help drive first-silicon success for complex networking and connectivity products. Experience leveraging AI-assisted engineering tools for verification productivity and debug acceleration is highly desirable.

Key Responsibilities

Provide technical leadership for verification of complex Ethernet and PCIe Switch SoCs, including datapath, control-plane, management, and CPU subsystems.
Define and drive verification architecture, methodologies, and best practices across projects and teams.
Lead verification of ARM/MIPS CPU subsystems and AMBA-based interconnect fabrics including AXI, AXI-Lite, AHB, and APB.
Architect scalable and reusable SystemVerilog UVM environments, agents, scoreboards, protocol checkers, and coverage frameworks.
Drive comprehensive verification planning and execution covering:
- PCIe subsystem functionality:
- Link training and LTSSM
- Enumeration and configuration space
- Error handling and recovery
- NTB and hot-plug support
- AMBA protocol verification:
- Corner-case and error scenarios
- CPU subsystem validation:
- Boot and reset sequences
- Register access and RAL integration
- DMA and memory interactions
- Interrupt and timer verification
Develop advanced constrained-random, directed, and scenario-based verification strategies for realistic traffic and system workloads.
Drive functional, code, assertion, and cross-coverage closure with metrics-driven methodologies.
Debug complex system-level issues spanning RTL, firmware interactions, AMBA fabrics, protocol layers, and UVM infrastructure.
Leverage AI-assisted tools for regression triage, debug automation, coverage analytics, and intelligent test optimization.
Collaborate closely with architecture, RTL, firmware, validation, emulation, and physical design teams.
Mentor and technically guide verification engineers across multiple experience levels.
Drive continuous improvement in:
- Regression infrastructure
- Reusability and scalability
- Simulation and debug productivity
Contribute to verification roadmap planning and methodology standardization across programs.

Requirements/Qualifications:

Required Qualifications

Bachelor's or Master's degree in Electrical Engineering or related field.
Typically 12+ years of ASIC/SoC verification experience with increasing technical leadership responsibilities.
Expert-level proficiency in SystemVerilog and UVM including:
- Advanced UVM architecture
- Reusable verification components
- Scoreboards and predictors
- Functional coverage modeling
- Sequence layering and virtual sequences
- UVM RAL methodology
Strong expertise in verifying AMBA-based interconnect fabrics (AXI, AXI-Lite, AHB, APB).
Proven experience verifying Ethernet and/or PCIe-based SoCs.
Strong understanding of ARM and/or MIPS CPU architectures and subsystem integration.
Deep understanding of:
- SoC architecture and integration
- Memory hierarchies and DMA
- Interrupt and coherency mechanisms
- High-performance interconnect behavior
Extensive experience with industry-standard simulators and debug tools:
- VCS
- Questa
- Xcelium
Strong scripting and automation expertise using Python, Perl, Tcl, or equivalent.
Excellent analytical, debugging, communication, and technical leadership skills.

Preferred Qualifications

Experience with:
- SoC-level verification closure
- Multi-IP subsystem integration
Experience integrating firmware/software-driven verification flows.
Exposure to AI/ML-based verification tools for:
- Intelligent debug
- Coverage optimization
- Automated failure classification
- Test generation
Experience building or driving metrics-driven verification environments.
Prior experience mentoring teams or leading technical initiatives across projects.