software security , Test automation, Sdlc, Agile, Selenium, Bdd, Test Strategy, AWS, Python, Azure, Tdd, Cloud Technologies, Automation Frameworks, Test Architecture, CI/CD, Quality Management System, Quality engineering practices

Arm, RTL fundamentals, RISC, Uvm, formal verification, systemverilog, SoC architectures, Digital Design

Systemc, Test Planning, C, Shell, Tcl, Verilog, Python, systemverilog, NoC bus and interconnect verification, assertions, transaction-level modeling, UVM-based testbench development, constrained-random verification, formal verification, power-aware verification

Verilog, SVA, formal verification, Assertions, Uvm, debugging complex RTL, systemverilog, Functional verification methodologies, testbench issues, Coverage