bist , boundary scan , DFT features, Scan Insertion, ATPG methodologies, advanced DFT techniques

boundary scan , Vcs, Python, Perl, Tcl, Scan Insertion, sdf debugging, DFT CAD development, Jtag protocols, DFT logic IP integration, p1687, p1500, EDA Tools, BIST architectures, Test static timing analysis, Tessent tool sets, Test Architecture Methodology, Infrastructure, memory BIST, TetraMax, Verilog design, Functional Verification, ATPG, Gate level simulation, Timing Closure, timing based simulations, TestMax

Java, C, Jtag, Perl, Python, MBIST, DFT methodologies, Pvt, SmarTest 7, ATPG, SERDES, 93K test method development, Advantest V93000, Scan

Java, C, Jtag, Perl, Python, DFT methodologies, MBIST, Pvt, SmarTest 7, 93K test method development, ATPG, SERDES, Advantest V93000, Scan