boundary scan , Vcs, Perl, System Verilog, Python, Tcl, Memory BIST, primetime, Logic Equivalency checking, TetraMax, Scan and BIST architectures, JTAG protocols, ATPG, EDA Tools, Tessent tool sets, TestMax

boundary scan , System Verilog, ATE patterns, Memory BIST, JTAG protocols, ATPG, Logic Equivalency checking, Post-silicon validation and debug, BIST architectures, P1687, Gate level simulation debugging