Similar Jobs - 69480022

Showing 4 jobs

DFT Engineering Technical Lead || ATPG, SCAN, JTAG, MBIST, TestMax, Tessent || Exp - 10+ years

10-12 yrs

Chennai, India

Skills:

boundary scan , Vcs, Perl, Python, System Verilog, Tcl, primetime, Logic Equivalency checking, Jtag protocols, memory BIST, TetraMax, Gate level simulation debugging, Scan and BIST architectures, ATPG, EDA Tools, Tessent tool sets, TestMax

Early Applicant

DFT Engineering Technical Lead || ATPG, SCAN, JTAG, MBIST, TestMax, Tessent || Exp - 10+ years

Cisco Live

10-12 yrs

Chennai, India

Skills:

boundary scan , Vcs, System Verilog, Memory BIST, JTAG protocols, ATPG, Logic Equivalency checking, Gate level simulation debugging, Scan and BIST architectures

Early Applicant

DFT Engineering Technical Lead || ATPG, SCAN, JTAG, MBIST, TestMax, Tessent || Exp - 10+ years

CISCO Credit

10-12 yrs

Chennai, India

Skills:

boundary scan , Vcs, System Verilog, Memory BIST, JTAG protocols, ATPG, Logic Equivalency checking, Gate level simulation debugging, Scan and BIST architectures

Early Applicant

ASIC DFT Engineering Technical Leader | ATPG, MBIST, SSN, SCAN | 12+ years

Cisco Home

12-14 yrs

Chennai, India

Skills:

boundary scan , Vcs, Static Timing Analysis, System Verilog, Post-silicon validation, DFT CAD development, Memory BIST, Logic Equivalency checking, P1687, Gate level simulation debugging, Scan and BIST architectures, Verilog design, ATE patterns, JTAG protocols, ATPG, Test Architecture Methodology

Early Applicant