Verilog, Microprocessors, Usb, Pcie, LINT, cdc, SoC clocking, pad ring, Design Compiler, Synthesis, Asynchronous interface, SDCC, RTL Coding, Low power SoC design, System-Verilog, constraint development, chip level floorplan, Memory controller designs, reset debug architecture, AMBA protocols, primetime, Axi, timing concepts for ASIC, APB, Timing Closure, SoC design and integration, AHB, Multi Clock designs