Golang, Distributed Systems, MLops, Kubernetes, Python, GenAI, MCP, ML model, Backend as a service, EKS

power integrity , Perl, Python, Tcl, Sta, primetime, Cadence Innovus, Tempus, EM IR analysis, Voltus

Machine Learning, Distributed Systems, Tensorflow, Pytorch, Predictive Analytics, Python, Big Data, Clustering, Deep Learning, MLops, Spark, GenAI, Telemetry Analytics, Data Pipelines, Random Forests, MLflow, Vector Databases, Time-Series Forecasting, AIOps, LLMs, Production AI Systems, anomaly detection, Cloud Data Architecture, Statistical Modeling

Shell, Perl, Scripting, Tcl, debug methodologies, automation using Python, Uvm, assertion-based verification, systemverilog, regression frameworks, coverage closure, formal verification, Functional Verification

Java, C, C++, MATLAB, Visual Basic, Perl, Python, Teradyne UltraFLEX, Spc, Oscilloscopes, Dft, Advantest V93K, ATPG, Logic analyzers, PMU, signal generators, ATE test development, Doe, RF Testing, SMUs

Routing, PEX, floorplanning, Plansr technologies, Physical Verification, LVS, Analog mixed-signal layout methodologies, Matching techniques, Post-layout verification, ERC, DRC, Analog Custom Layout, Cadence Virtuoso

Devops, Jenkins, Git, Docker, Kubernetes, Python, AgenticAI frameworks, R, AI ML engineering, CI CD tools

UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), C, C++, Shell, Pcie, Perl, Arm, Python, Tcl, Systemc, MCU, Hardware Emulation Platforms, RISC-V, UCIe, systemverilog, Verification Methodology, AMBA, Axi, Formal Model Equivalence Checking Tools, formal verification, VC Formal

temperature sensors , bandgap references , DNL, ADEXL, op-amps, INL, biasing circuits, Layout XL, THD, precision analog circuits, CMOS technologies, DC operating point, noise, Stability, LDOs, mixed-signal circuit design, AMs, Cadence Virtuoso suite, Spectre, Sigma-Delta converters, Schematic Maestro, AC simulations, frequency response, ip development, mismatch analysis