In most instances, this position requires in-person interviews as part of the hiring process.Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel.
5 years of experience in micro-architecture and design of SoCs and subsystems.
4 years of experience in people management, developing employees.
Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience in SoC designs and integration flows.
Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
Knowledge of high-performance and low power design techniques.

About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

Lead SoC/SS integration team. Drive development of complex IPs and Subsystems along with a team of engineers in the Bengaluru design organization.
Own microarchitecture and implementation of IPs and subsystems.
Work with Architecture, Firmware and Software teams to drive feature closure and develop microarchitecture specifications.
Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.
Identify and drive Power, Performance and Area improvements for the domains owned.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

Silicon SoC Integration Design Lead, Google Cloud