Scripts, Automation Tools, Verilog, Shell scripting, C, Jtag, Python, debug activities, Digital Design, hardware verification methodologies, FPGA synthesis, systemverilog, Ai, hardware-software interactions, Implementation, ML concepts, hardware debugging tools, RTL design concepts, protocol analyzers, ASIC development flow, logic analyzers, Github Copilot, FPGA Architecture, Timing Closure, Embedded Systems

.NET, automation, Java, Github, Devops, shell scripting, Python, Gcp, Terraform, Go, infrastructure-as-code, SRE, application enablement

boundary scan , Jtag, RTL Coding, Digital design fundamentals, Low Power Checks, LINT, ASIC design flow, Analog Phy DFT, cdc

RF Planning, Unix, Bash, Shell, Eap, Perl, Linux, Switching Protocols, Automation Scripting, Python, Radius, WPA3, Rf Survey, Optimization, Enterprise wireless architecture, 802.1X

SPICE simulation, Timing Analysis Concepts, Correlation methodologies between characterization tools and STA flows, Design rule checks, Standard cell library characterization