static timing analysis, Automation Frameworks, Verilog, low-power implementation methodologies, design constraints, generative AI tools, functional validation, AI-assisted engineering technologies, systemverilog, Rtl Design, Logic Synthesis, EDA Tools, Timing Closure

Debug Root Cause Analysis, Coverage Sign-Off, Assertion Formal Verification, Testbench Development, Verification Planning, Uvm, SoC Verification, systemverilog

C, Makefile, Soc Architecture, Windows, Perl, Linux, Verilog, Python, System Verilog, Systemc, ASIC Design Flow, debugging skills in functional simulations, UVM testbenches, automating workflows in a distributed compute environment, Asic Design Verification

C, Makefile, Soc Architecture, Windows, Linux, Perl, Verilog, System Verilog, Python, Systemc, ASIC Design Flow, debugging skills in functional simulations, UVM testbenches, automating workflows in a distributed compute environment, Asic Design Verification