cadence schematic capture , Hspice, high-speed custom digital design flows, AMs, Cadence Virtuoso, Spectre

Routing, PEX, floorplanning, Plansr technologies, Physical Verification, LVS, Analog mixed-signal layout methodologies, Matching techniques, Post-layout verification, ERC, DRC, Analog Custom Layout, Cadence Virtuoso

Spi, I2c, Silicon Bring-Up, Control Systems Fundamentals, Layout Reviews, PEX Simulations, PMIC, MIPI, I3C, High-Voltage Circuit Designs, Simplis AMS, Cadence Virtuoso, Converter Control Architectures, Analog Design, Post-Layout Verification, Simulation, monte carlo simulation, Worst-Case Corner Analysis, Spectre, Integrated Power FETs, schematic capture, Circuit Design, Power IC Design Flows, characterization, Gate Drivers

transistor-level design and simulation, PEX, post-layout verification, LVS, noise analysis, Analog Circuit Design, Spectre, advanced CMOS technology nodes, DRC, layout sensitivity, linearity matching, mixed-signal IC design, Cadence Virtuoso

bandgap references , temperature sensors , Dll, Process Monitor, AI proficiency, Parasitic modeling, design validation, verification processes, Oscillators, Claude, agentic AI models, modeling and simulation, Comparators, Analog Test Mux, Charge Pumps, CMOS Amplifiers, LDOs, IO Buffers

Bias generators, Bandgaps, Simulation verification, Cadence Virtuoso Spectre, ADCs, SPICE-based simulations, Analog Circuit Design, Power-management ICs, DRC LVS extraction, MOSFET physics, DACs, Silicon debug support, Driver amplifiers, DC-DC converters, Post-layout verification, Sensing circuits, Gate drivers, Error amplifiers, Charge pumps, LDOs, Level shifters, Analog Layout