PERL, Verilog, System Verilog, Tcl, Uvm

Ovm, Database Management, Verilog, System Verilog, silicon debug, verification management tools, formal property checking tools, Uvm, memory controller protocols, assertion and metric-driven verification, Synopsys VCS, gate level simulation, power verification, reset verification, Cadence IES, contention checking, calibration board skew and jitter modeling

Ovm, Database Management, Verilog, System Verilog, high speed interface verification, silicon debug, verification management tools, formal property checking tools, Uvm, Synopsys VCS, gate level simulation, power verification, Cadence IES, reset verification, contention checking, metric-driven verification

code coverage , C, Shell, Verilog, Debugging, Flash, Python, System Verilog, Perl, Tcl, interconnect, Memory, UVM methodology, Microprocessor architecture, clocking system modes, power management, SoC Verification, constrained random methodologies, Metric Driven Verification, Rom, formal verification methodologies, Axi, MRAM, AHB, Ram