Makefile, Perl, Route, Scripting, Python, Tcl, Sta, CTS, debug skills, Mentor, Cadence, Physical Design, Physical Verification, EMIR, PNR, ML techniques, SDC coding, Timing Closure, Synopsys

Route, Rtl Design, SDC coding and debug, Synthesis, ML techniques and algorithms in physical design, Physical Verification, Place and route timing closure, AMD block TileBuilder, Low power physical design implementation flows

Makefile, Perl, Route, Python, Scripting, Tcl, Sta, CTS, debug skills, Mentor, Cadence, Physical Design, Physical Verification, EMIR, PNR, ML techniques, Timing Closure, SDC coding, Synopsys