static timing analysis, Perl, Verilog, Python, Tcl, Rtl Design, Synthesis, Dft, ATPG, systemverilog

Tcl, Python, Perl, Spice simulations, ASIC back-end flows, Timing Constraints, AOCV, Monte Carlo analysis, noise, cross-talk, STA fundamentals, Hspice, POCV concepts, CTS, Innovus, ICC2, primetime, Tempus, Signal Integrity, Parasitic Extraction, scripting proficiency, STA tools, FineSim