Shell, Perl, Python, Tcl, Cadence Xcelium, Mentor QuestaSim, PCI Express, Uvm, systemverilog, Synopsys VCS, Assertion-Based Verification, Constrained Random Verification, Functional Verification

Verilog, Scripting, checkers, Uvm, assertion-based verification, coverage driven verification methodology, bus functional models, systemverilog, scoreboards, VMM, monitors, functional coverage

Perl, Python, Tcl, Functional Coverage, Uvm, SVA, systemverilog, ASIC SoC Subsystem IP verification

Usb, DDR, Perl, Pcie, Ethernet, Python, Tcl, Uvm, coverage-driven verification, systemverilog, digital design RTL understanding, AMBA, MIPI, SVA

C, Perl, Python, Tcl, IP-XACT, Uvm, UPF, systemverilog, GLS, Axi, SystemRDL, APB, Tk, AHB, RAL

Pcie, Regression Testing, Verilog, Ethernet, assertions, Uvm, systemverilog, functional coverage, constrained-random verification

C, C++, Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, Post-silicon debugging, RTL design and verification flows, Simulation Tools, JTAG protocols, Digital Design, Assembly language programming

Debugging, Ovm, Verilog, System Verilog, Problem-solving skills, Functional Verification Coverage, Uvm, formal verification, DDR-PHY Design Verification, Design Verification of complex IPs, Low Power Verification, Gate Simulation

Computer Architecture, C, Assembly Language, Vcs, Perl, Verilog, Python, System Verilog, Computer Engineering, Raven, UVM methodology, ACK, Microelectronics, Questa, Electrical Engineering