Debugging, Ovm, Verilog, System Verilog, Problem-solving skills, Functional Verification Coverage, Uvm, formal verification, DDR-PHY Design Verification, Design Verification of complex IPs, Low Power Verification, Gate Simulation

Perl, Python, Tcl, DDR5 LPDDR5 verification, SVA, functional coverage, VIP emulation, DDR PHY verification, SystemVerilog UVM, FPGA prototyping, debug and root-cause analysis