Perl, Vcs, Python, Tcl, Verdi, Xcelium, ARM CPU Subsystem CPUSS verification, Uvm, systemverilog, AMBA CHI coherency and interconnect protocols

SV, PSS, Uvm

C, Verilog, Ovm, Perl scripting, Python, System Verilog, VMM, Axi, Uvm, AHB

rtl verification , Debugging, AMS IP Verification, AMS IP Integration, SoC-Level Verification, Sub-System Verification, PDL Test Case Development, Gate-Level Simulation, Timing Simulation, Virtual Tester Simulation, Tessent DFT, DFT Pattern Generation, Pattern Simulation, Testbench Bring-Up

Perl, Python, Tcl, Pcie, Cadence Xcelium, Uvm, systemverilog, Synopsys VCS, AMBA AXI, CPF, UPF

code coverage , C, Shell, Perl, Verilog, Debugging, Python, System Verilog, Tcl, UVM methodology, Metric Driven Verification, formal verification methodologies, assertions, constrained random methodologies, functional coverage

Soc Architecture, System Verilog, scoreboarding, digital design fundamentals, UVM methodology, ASIC SoC functional verification, SoC-level verification, constrained-random stimulus, assertions, functional coverage, SVA, performance verification