Computer Architecture, Logic Design, Perl, Verilog, Python, LINT, high performance computing, Digital Signal Processing Techniques, HLS, Synthesis, VHDL, Physical Design tools

scripting (Python, Shell), Digital Logic Design, Tcl, Makefile, Perl, Algorithm Development, Verification Tools, IP SoC development methodology, EDA Tools, RTL Coding

Unix, Ilm, Linux, Python, Tcl, QRC models, back-annotation, Multi-Vt, SPEF correlation, Cadence Tempus, Innovus, glitch analysis, Tempus SI, voltage island timing, ETM

Routing, Python, Tcl, Sta, CTS, Signoff, floorplanning, EM Noise, LVS, Power Planning, IR Drop, Physical Verification, Eco, Physical Design, Placement, Timing Closure, Si, DRC

C, C++, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, acceleration HLS tools process, UVM testbenches, automating workflows in a distributed compute environment, simulation profile efficiency improvement, debugging firmware and RTL code using simulation tools, UVM based verification frameworks, TLM

Vcs, Tcl Scripting, Python, cdc, Xcelium, QuestaSim, RTL lint, systemverilog, quartus, RDC, Vivado, AMBA AXI AHB APB protocols

Verilog, digital RTL design, analog–digital co-simulation, Spice, systemverilog, Verilog-A

Perl, Python, Tcl, Innovus, Calibre, Assura, ICC2, Cadence, Synopsys, ICV

MATLAB, Python, sequential design in Zemax, MTF, paraxial design, aberrations, ZOS-API, lens data editor, Zemax OpticStudio, stops and pupils, compact imaging systems, illumination design, smartphone camera modules, merit functions optimisation, ophthalmic optics, tolerancing, geometric optics, stray-light analysis, 3D Printing, optical bench work