DDR, Pcie, Nvme, Verilog, System Verilog, scoreboard assertions, functional coverage coding, Axi, RTL debugging, Uvm, AHB, code coverage analysis

Python, Perl, Shell, systemverilog, Uvm, Verilog-A, Verilog-AMS, Wreal, Cadence Virtuoso AMS Designer

Gate-Level Simulation (GLS), Design-for-Test (DFT), Perl, Python, systemverilog, Synopsys VCS, Siemens Questa, Verdi, Cadence Xcelium, DVE, Uvm, UPF