Regression management, Runsets decks and automation flows, Foundry decks and PDK updates, Hierarchical verification, Tapeout readiness reviews, Antenna density and reliability checks

Physical Design Verification, Synthesis, Layout Closure, RTL2GDSII Concepts, Tapeouts, Full Chip Integration, CTS Timing Convergence, Physical Implementation, VLSI Design Concepts, Place Route

Tcl, Unix Shell, Python, Perl, ICV, LVS, Cadence Virtuoso, DRC, Calibre, PERC