Cadence Virtuoso, analog and mixed-signal circuit design, high-speed analog architectures, Signal Integrity, jitter, Spectre, advanced CMOS technology nodes

Git, JIRA, Python, Make-based build flows, silicon bring-up, Microcontrollers, architecture and development of firmware modules, bare-metal embedded firmware development, firmware debugging tools

Ansys, Silicon Validation, PERL, Debugging, Python, analog simulation, lab equipment, Cadence, Analog Circuit Design, design for test, Mixed Signal Design, EDA Tools, CMOS technology, silicon bring-up, virtuoso, Synopsys, low-power design techniques

Analog Circuit Design, Design Verification, Monte Carlo analysis, Modern CAD tools, Silicon validation and debug, Analog layouts, Simulation and Verification, Transistor level design flow, Schematic generation

power converters , post layout parasitic extraction, Monte Carlo analysis, bandgaps, sensing circuitry, Simulation, block level topology selection, Spectre, switching regulators, schematic generation, DACs, VHDL, charge pumps, Amplifiers, physical layout management, Spice, Transistor Level Design, Comparators, IC CAD tools, analog and mixed signal design, precision analog control

Debugging, Test architecture definition, Scan Insertion, Timing constraints for test mode timing closure, Scan and ATPG for different fault models, LEC checks, Zero delay and timing simulations, RTL changes for DFT, Post silicon bring up, DFT ownership, IEEE1687 iJTAG compliant ICL PDL for functional manufacturing tests, Boundary scan ACJTAG IEEE 1500 implementation and verification, Low power CLP checks

Pll, compensation techniques, transistor capacitor matching, transistor level circuit design, EDA Tools, analog mixed signal design, SERDES, high-speed TX, noise analysis