Python, Tcl, Low power or processor designs, Toplevel physical implementation

Tcl Scripting, Ovm, Unix Shell Scripting, DDR, Pcie, Perl, Verilog, Debugging, System Verilog, test bench development, CMOS logic design, IC chip design development flow process, CMOS device operation and characteristics, Simulation, verification plans, Uvm, Circuit Analysis, CAE CAD tools, Axi, VHDL, AHB, Circuit Design, coverage assertion driven verification

regulators , Routing, Design validation, Parasitic modeling, Ai, Bandgap reference, Comparators, Tape-out revisions, Industry standard simulators, Floor-planning, CMOS Amplifiers, Memory Logic Analog circuits, Modeling and simulation, Verification processes, Charge-pumps, Placement, Layout process, Reticle experiments, Analog Power Management IPs, Voltage Current reference

layout verification , static timing analysis, Synthesis, coverage analysis, electrical rule checking, SOC design, formal equivalence verification, physical design implementation, Power Clock Distribution, structural design checking, Place And Route, power and noise analysis, RTL to GDS, Floor Planning, static and dynamic power integrity, Dft, EDA Tools, Timing Closure, multiple power domain analysis, Clock Tree Synthesis

Routing, Python Scripting, Tcl Scripting, primetime, floorplanning, Tempus, Cadence Innovus, Calibre, Physical Verification, Physical Design, Timing Closure, Placement, ECO Implementation, ICV, Synopsys ICC2