Perl, Python, Tcl, Timing Closure STA, RTL-to-GDSII Execution, Red Hawk, Programming Scripting, Fusion Compiler, LEC, Tempus, Cross-Functional Collaboration, Physical Formal Verification, Innovus, Calibre, primetime, PPA Optimization, EDA Tools, VCLP

Java, C, Python, BIOS, Uefi, C++, Software firmware test automation, BMC firmware, Automated software firmware test suites, Software firmware validation, Continuous integration and continuous deployment

Scripting, EDA Tool Proficiency, Cross-Functional Collaboration, Risk Issue Management, Team Leadership Mentorship, SerDes IP Integration, Architecture Methodology, Technical Ownership Project Planning, RTL-to-GDSII Execution, Advanced Technology Nodes, Stakeholder Vendor Alignment, Timing PPA Closure, SoC-Level Physical Design

bist , C, Vcs, Verilog, Python, Asic verification, Genus Design Compiler, digital timing constraints, XCelium, high-speed SerDes, SOC interconnect fabrics, ASIC tool flows, Scan Insertion, DFT methodologies, Timing Analysis, systemverilog, FPGAs, ASIC synthesis, Axi, AMBA, Timing Constraints, ATPG, APB, Questa, microcontroller platforms, Cadence Virtuoso, AHB

.NET, .Net Core, C#, Graphql, Kafka, Css3, Angular, Automated Testing, Git, Typescript, Javascript, Gcp, Docker, Html5, ASP.NET, Distributed Systems, Azure, Kubernetes, AWS, NoSQL databases, Microservices architecture, CI/CD pipelines, Service Bus

arm architecture , Uart, Verilog, I2c, Pcie, Flash, digital ASIC design, system memory hierarchy, AMBA bus protocols, constraints development, systemverilog, low power methodology, system debug infrastructure, multi-core SOC designs, DC DC-T based synthesis, RTL level checks, DRAM, ARM v8 and v9 specifications, SSP, ARM based ecosystem components