Static timing analysis, Perl, Python, Tcl, ASIC DFX, DFx methodologies, Design Compiler, BSCAN, MBIST, DFX Design Architect, SSN, Timing Closure, Synthesis, spyglass, DFT implementation, Tessent, ATPG, Scan, TestKompress, IJTAG

Perl, Python, Tcl, DFx methodologies, Design Compiler, Fusion Compiler, BSCAN, MBIST, DFX Design Architect, SSN, spyglass, Tessent, ATPG, Scan, TestKompress, IJTAG

Makefile, Windows, Linux, Perl, Verilog, Ruby, Systemc, C++, HLS tools, UVM testbenches, TLM, Asic verification, Graphics pipeline knowledge, UVM based verification frameworks, Simulation Tools, systemverilog

Makefile, Windows, Perl, Linux, Verilog, Ruby, Systemc, C++, HLS tools, UVM testbenches, UVM based verification frameworks, TLM, Asic verification, Graphics pipeline knowledge, Simulation Tools, systemverilog