Version Control Systems, Soc Architecture, Asic Design Verification, BFMs, UVCs, Regression automation, Functional and code coverage methodologies, Uvm, SoC IP verification environments, systemverilog, VIPs

C, Makefile, Soc Architecture, Windows, Linux, Perl, Verilog, System Verilog, Python, Systemc, ASIC Design Flow, debugging skills in functional simulations, UVM testbenches, automating workflows in a distributed compute environment, Asic Design Verification

Shell, Version Control Systems, System Verilog, Python, Scripting, Soc Architecture, Perl, performance features, functional and code coverage methodologies, Advanced SystemVerilog, X86 based SOC DV, Uvm, coverage closure, Security, BFMs, UVCs, power management, regression automation, memory subsystems, Debug, interconnects, SoC IP verification environments, Asic Design Verification, debugging skills, SoC verification methodologies, simulation and verification tools, VIPs

C, C++, Makefile, Windows, Soc Architecture, Linux, Perl, Verilog, Python, Systemc, HLS tools, ASIC Design Flow, UVM testbenches, Asic Design Verification