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Showing 5 jobs
Skills:
Perl, Verilog, Python, Tcl, Physical Design, Signoff, VHDL, Full-chip aspects, IP integration, Timing Verification
Skills:
Python Scripting, Verilog, Physical Design, VHDL, Timing verification and signoff, Low Power Checks, Physical Verification
Skills:
Verilog, Python Scripting, Physical Design, VHDL, Low Power Checks, Timing verification and signoff, Physical Verification
Skills:
Shell, Tcl Scripting, Python, Routing, Perl, Sta, CTS, Signoff, OCV, primetime, Fusion Compiler, Crosstalk, Tempus, Cadence Innovus, Signal Integrity, LVS, IR Drop, Physical Verification, MCMM, POCV, Setup Hold, RTL-to-GDSII Physical Design flow, floorplanning, Post-route Optimization, Placement Optimization, EM, Power Planning, Eco, Timing Closure, DRC, AOCV, Synopsys ICC2
Skills:
Synthesis, physical verification closure, Formal, Timing Closure, block chip level implementation from Netlist to GDS, scripting skills – TCL
