Ovm, Database Management, Verilog, System Verilog, silicon debug, verification management tools, formal property checking tools, Uvm, memory controller protocols, assertion and metric-driven verification, Synopsys VCS, gate level simulation, power verification, Cadence IES, reset verification, Cadence Jasper, contention checking, calibration board skew and jitter modeling

Ovm, Verilog, Contention checking, Debug environments, Uvm, Simulation Tools, Power verification, Synopsys VCS, Reset verification, Assertion and metric-driven verification, Cadence IES, Gate level simulation, Verification management tools

Ovm, Verilog, Uvm, Synopsys VCS, Cadence IES, Power verification, Reset verification, Assertion and metric-driven verification, Gate level simulation, Contention checking, Verification management tools, Debug environments, Simulation Tools