Similar Jobs - 69369624

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Lead RTL Design & Validation Engineer with DDR protocols exp

9-11 yrs

Hyderabad, India

Skills:

DRAM memory controller initialization code, Logic analyzers, Compliance packages, DDR memory controller calibration, Calibration algorithms

Early Applicant

Lead RTL Design & Validation Engineer with DDR protocols exp

AMD Maquinaria

9-11 yrs

Hyderabad, India

Skills:

JEDEC standards, RTL design in Verilog, Circuit timing STA, Digital Design, Memory controller initialization code, Embedded experience, Memory subsystem

Early Applicant

Lead RTL Design & Validation Engineer with DDR protocols exp

AMD Ventures

9-11 yrs

Hyderabad, India

Skills:

JEDEC standards, RTL design in Verilog, Circuit timing STA, Digital Design, Memory controller initialization code, Embedded experience, Memory subsystem

Early Applicant