Windows, Perl scripting, Linux, Python, System Verilog, Tcl, RTL design in Verilog, DFT technologies, UPF, primetime, Cadence Conformal, spyglass, Timing Constraints, Synopsys Design Compiler, Questa CDC, VCS simulation

Perl scripting, System Verilog, Windows, Version Control Systems, Linux, Verilog, Python, Tcl, primetime, DFT technologies, Synopsys Design Compiler, SOC design, UPF, Rtl Design, spyglass, Cadence Conformal, Timing Constraints, ASIC Design, Questa CDC, VCS simulation

Windows, Perl scripting, Version Control Systems, Linux, Verilog, System Verilog, Python, Tcl, DFT technologies, SOC design, UPF, Rtl Design, primetime, spyglass, Cadence Conformal, Timing Constraints, Synopsys Design Compiler, ASIC Design, Questa CDC, VCS simulation