Design for Testing (DFT), rtl development , System on a Chip (SoC) designs and integration, Verilog, Python, Perl, power analysis, LINT, processor design, cdc, arithmetic units, power closure, memory hierarchies, test plan and coverage analysis, FV, UPF checks, simulation debug, silicon bring-up, micro-architecture, bus architectures, Synthesis, ASIC SoC design verification, Timing, systemverilog, subsystem integration, accelerators, low-power design techniques