Tcl, C, Systemc, Test Planning, Shell, Verilog, Python, Debugging, formal verification, Assertions, systemverilog, Transaction-level modeling, NoC bus and interconnect verification, Power-aware verification, UVM-based testbench development, Constrained-random verification

Debugging, C, Shell, Tcl, Verilog, System Verilog, Python, Perl, directed and constrained random methodologies, UVM methodology, Metric Driven Verification, functional and code coverage, assertions, formal verification methodologies

Arm, SoC architectures, formal verification, RTL fundamentals, Digital Design, Uvm, RISC, systemverilog