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Showing 3 jobs
Skills:
C, Perl, Verilog, Python, Tcl, formal verification, VHDL, Uvm, systemverilog, constrained-random verification
Skills:
Python, Spi, C, Systemc, Uart, Shell, Tcl, Verilog, I2c, Ethernet, SVI3, systemverilog, NoC bus and interconnect verification, AHB, UVM-based testbench development, DMA, formal verification, power-aware verification, Axi
Skills:
Verilog, SVA, formal verification, Assertions, Uvm, debugging complex RTL, systemverilog, Functional verification methodologies, testbench issues, Coverage
