arm architecture , Test Plans, C, C++, ACE lite or CHI bus protocols, CPU architecture, Coherent and non-coherent fabric IPs and protocols, PCIe Controller PHY IPs and protocols, DDR protocols, pre-silicon SoC verification, Memory Controller PHY IPs, performance verification, Coverage, checkers, Emulation, test generators, test benches

Test Plan Creation, Regression Analysis, Uvm, formal verification, coverage-driven verification, systemverilog, SV assertions

C, Perl, Verilog, Gdb, Python, Indago, SOC design, Cadence

Spi, C, Uart, Tcl, Verilog, Bash, I2c, Python, Pcie, Perl, LPDDR, Uvm, i2s, systemverilog, DFX Verification, AHB, APB, Axi

Shell, Perl, Verilog, Automation Scripting, Python, Tcl, SVA, Protocol verification, Formal verification methodologies, systemverilog, RTL analysis, Temporal logic