Verilog, Integration, System Verilog, ATB-AMBA protocol, SoC development, Uvm, Debug architecture, Gate Level simulations, verification testbench, Axi, ASIC Design, Power aware simulations, Verification, Validation, AHB

Bus protocols - APB, C, Usb, Uart, Spi, Test Plan Creation, Pcie, I2c, System Verilog, Bus interconnects, Checkers, i2s, Uvm, Functional coverage, DP, Sd, AHB, Verification methodology, Gate-level simulations, Scoreboards, Gate Level Power-Aware simulations, Axi

Usb, DDR, Perl, Pcie, Ethernet, Debugging, Python, Tcl, Uvm, systemverilog, constrained-random verification, coverage closure, functional coverage assertions, CXL, SVA

Perl, Python, Formal Verification methodologies, Axi, APB, JasperGold, AMBA protocols, VC Formal, Uvm, AHB, systemverilog